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TNT4882 GPIB Interface ASIC circuit

Published on Oct 28 2010 // Micrcontroller circuits

TNT4882 GPIB Interface ASIC circuit

Abstract: TNT4882 U.S. NI GPIB interface, the company introduced a special chip. This paper describes its internal structure, the external clock circuit and register some important given TNT4882 GPIB interface design programming for the basic ideas and considerations.
1 Overview
NI TNT4882 companies in the United States a single chip, high-speed, listening / speaking function of both the GPIB (General purpose interface bus) interface to ASIC. It integrates a Turbo488 (high speed circuit) and the NAT4882 (IEEE488.2-compliant circuit), and has many new features, can be compatible with ANSI IEEE Standard 488.1 and ANSI IEEE Standard 488.2 specification, which can provide a complete GPIB system solution. In order to achieve higher transmission rates. TNT4882 FIFO buffer with a single-chip circuit design, and its built-in 16 enhanced IEEE 488.1-compliant transceivers can be connected directly GPIB bus, in order to achieve HS488 transfer mode (a new high-speed GPIB transfer mode). In the compatibility, it uses the past µPD7210, TMS9914A register settings in the fully compatible, users can use the code previously transplanted directly to the TNT4882 on. Also, it contains many new features Turbo488 circuit and can also reduce to some extent the cost of the software. In addition, TMT4882 also has a flexible CPU interface for easy connection to a variety of 16-bit or 8-bit microprocessor, and CPU issued messages and signals into the appropriate GPIB messages and signals, in order to achieve GPIB devices and CPU and communication between the memory.

Figure 1 Block diagram of two-chip model Click to enlarge
2 internal structure and external clock circuit
The internal structure of 2.1 TNT4882
TNT4882 the internal structure of their working patterns vary. Mode can be divided into single-chip mode and dual-chip mode two, and two-chip model can be divided into Turbo +7210 mode and Turbo +9914 mode. Mode selection and conversion by the register settings to determine the different operating mode determines the FIFO is connected with the GPIB, the state register and access attributes.
In the two-chip operating mode, NAT4882 equivalent µPD7210 (Turbo +7210 mode) or TMS9914A (Turbo +9914 mode), but more powerful. Structure and working process at this time shown in Figure 1. Current GPIB write data, CPU first to write data to the FIFO in TNT4882 by the transfer of data from the FIFO state machine circuit spread NAT4882, NAT4882 circuit then sent to the data on the GPIB; and when to read data from the GPIB , the process is just the opposite.
In the single-chip operating mode, FIFO can be directly connected with the GPIB transfer without the need for state machine, its structure shown in Figure 2. At this point, TNT4882 in the register set and the Turbo +7210 mode similar.
2.2 The external clock circuit
TNT4882 work requires driving 40MHz clock to generate the clock signal in two ways: First, the CMOS with 40MHz crystal, the crystal oscillator output pin connected to the TNT4882 the XTALI and XTALO pin floating; the second is the use of Figure 3 shows the external clock circuit.

Figure 2 Block diagram of single-chip mode the external clock circuit Figure 3 TNT4882 Click to enlarge
About 3 register
TNT4882 the number and types of internal registers are many, but in a different mode, the register of the situation is different. This single-chip mode and only the most basic GPIB operation with a number of registers on a brief introduction.
Note that, TNT4882 internal registers are 8 bits. Therefore, the control of each register must also be 8-bit word. The address is usually TNT4882 register base address registers with each corresponding offset. TNT4882 base address determined by the hardware circuit, each register corresponding to the offset is fixed, ranging from 0 to 0x1F. There are three types of registers: read-only, write-only and read / write. Table 1 lists some of the more important of the register type.
Table 1 TNT4882 part of the register
Offset register Type abbreviation
Write-only command register CMDR1C
Auxiliary Mode Register AUXMR0A write-only
Continuous polling mode write-only register SPMR06
Handshake Select Register HSSEL0D write-only
Enable high-speed write-only register HIER13
Write-only multi-function register MISC15
Address Mode Register ADMR08 write-only
Write-only address register ADR0C
Write-only interrupt register 0IMR01D
Write-only interrupt register 1IMR102
Write-only configuration register CFG10
Write-only bus control register BCR1F
Read-only status register BSR1F bus
Address read-only status register ADSR08
FIFO buffer AFIFOA19 read / write
FIFO buffer BFIFOB18 read / write
0CNT014 count register read / write
1CNT116 count register read / write
2CNT209 count register read / write
3CNT30B count register read / write
4 software programming
TNT4882 is a need for software programming of integrated circuits. Its internal state of each register mark chips and GPIB decisions or work status. In the GPIB interface design, only by programming the correct equipment on the register in order to achieve a variety of GPIB operation. The following are the basic ideas and programming considerations.
4.1 Chip Initialization
The most typical initialization procedure should perform the following tasks:
(1) reset the TNT4882 Devices Turbo488 circuit;
(2) TNT4882 set Turbo +7210 mode;
(3) TNT4882 set Microcontroller mode;
(4) to Local Power-On signal is valid;
(5) configuration TNT4882 GPIB operations that prepare the specific task is to set TNT4882 the GPIB address, set the initial serial poll response, set the initial parallel poll response, clear or set the interrupt, set the GPIB handshake parameters.
(6) Clear Local Power-On signal, begin GPIB operation.
The work is programmed to take into account the basic principles to achieve various functions, designed according to their actual needs, the TNT4882 appropriate programming, and there is no need to complete the settings for each function.
4.2 GPIB data transfer
Conducted by TNT4882 GPIB data transmission, undergoes initialization, data transfer and termination of the three stages of transmission, transmission initialized as follows:
(1) correctly set TNT4882 address mode. Before the GPIB write operations, say the state should be set TNT4882; in GPIB read before listening to TNT4882 set state;

(2) empty the FIFO, to prepare for data transmission;
(3) write to the configuration register to set the correct control word transmission parameters;
(4) To transmit characters written to complement the number of count registers;
(5) If necessary, you can set the parameters and use the DMA mode DMA transmission;
(6) According to the needs of a reasonable set or clear the interrupt;
(7) to the TNT4882 sent transfer command.
Initialize the transfer is complete, the system can transfer data between memory and the GPIB. At this point, only to be considered how to coordinate the work between memory and FIFO, and FIFO and the TNT4882 will automatically manage data transfer between the GPIB. Can usually choose between two transmission: DMA control methods and procedures. If you are using DMA mode, the transmission must be properly initialized when TNT4882 set. If you use the program control, it would take control program designed to manage the data transmission. The basic flow control program shown in Figure 4.
When the data transfer is terminated, following a few steps should be:
(1) send a stop command to the TNT4882;
(2) If using DMA mode, the need to prohibit external DMA controller;
(3) clear all interrupt settings.
5 Conclusion
Use TNT4882, in addition require an external 40MHz external clock outside a virtually without any other auxiliary circuit, thus greatly simplifying the interface circuit design and development. Proved by the author: TNT4882 is a cheap, high-performance ASIC GPIB interfaces, GPIB interface design is the ideal choice.