Abstract: A micro-controller 8051 and 82527 independent CAN bus controller core component of the CAN-bus design of smart sensor nodes, and gives the hardware schematics and initialization procedures.
Keywords: CAN bus 82527 single chip data acquisition intelligent node
CAN (Controller Area Network, Controller Area Network) are industrial field bus, a German company Bosch 80 in the early 20th century as a solution to many modern vehicle control and test equipment developed for data exchange between a communication protocol. November 1993, ISO issued a formal high-speed communication control LAN (CAN) international standards (ISO11898). CAN bus system in the collection of field data completed by the sensor, at present, the sensor with CAN bus interface type is not much more expensive price. This paper presents a 8051 and 82,527 by the independent CAN bus controller core components of the intelligent node circuit, formed on the basis of the common sensor can receive 8-channel analog input and smart sensor nodes.
1 Introduction independent CAN bus controller 82527
Intel 82527 is an independent production company CAN bus controller, through the parallel bus with Intel and Motrorola controller interface; support the CAN 2.0B standard procedures, with receiving and sending packet filtering can be done. 82527 by CHMOS 5V process, 44-pin PLCC package temperature is -44 ~ +125 ?, the pin arrangement and definitions see reference .
(1) 82527 of the clock signal
82527’s run by two kinds of clock control: the system clock SCLK and register clock MCLK. Obtained by an external crystal SCLK, MCLK SCLK frequency of access. CAN bus bit timing according to the frequency of SCLK, while the MCLK clock for the register operation. SCLK frequency can be equal to the external crystal XTAL, it can be the frequency of 1 / 2; MCLK SCLK frequency or the frequency can be equal to 1 / 2. After system reset the default setting is SCLK = XTAL / 2, MCLK = SCLK / 2.
(2) The operating mode of 82527
82527 5 working modes: Intel mode 8-bit time-multiplexed mode; Intel 16-bit time division multiplexing manner mode; serial interface mode; non-Intel way of 8-bit time-multiplexed mode; 8-bit non-time division multiplexing mode. In this paper, Intel 8-bit time division multiplexing manner mode, then 82,527 feet of 30 and 44 grounded.
(3) 82527 register structure 
82527 register address is 00 ~ FFH. The following description is given according to need to register.
Control Register (00H):
CCE – change the configuration allows bit, active high. This bit is valid on the configuration registers allow the CPU 1FH, 2FH, 3FH, 4FH, 9FH, AFH write.
EIE – Error interrupt enable bit, active high. The general set a bit, when the number of bus error exception generated interrupt CPU.
SIE – status change interrupt enable bit, active high. This bit normally set to 0.
IE – Interrupt Enable bit, active high.
INIT – allow software initialization bit, active high. This bit is valid, CAN stop sending and receiving messages, TX0 and TX1 is the recessive level 1. Off the bus in the hardware reset and when the bit is set.
CPU Interface register (02H):
RSTST – hardware reset status bits. This bit is written by the 82527, for 1 hardware reset activation, does not allow access to the 82527; to 0 to allow access to the 82527.
DSC – SCLK divider bits. This bit is 1, SCLK = XTAL / 2; to 0, SCLK = XTAL.
DMC – MCLK divider bits. This bit is 1, MCLK = SCLK / 2; to 0, MCLK = SCLK.
PWD – Power-down mode enable bit, active high.
SLEEP – Sleep Mode Enable bit, active high.
MUX – low-speed physical layer multiplexing flag. This bit is 1, ISO low speed physical layer activation, PIN24 = VCC / 2, PIN11 = INT # (# that negated); the bit is 0, PIN24 = INT #, PIN11 = P2.6.
CEN – clock output enable bit, active high.
Standard Global Mask Register (06 ~ 07H). This register is used with a standard packet identifier, or set to 0 packets XTD register. The approach is called the message receiver filtering. When a is 1, the corresponding message identifier bits must match; to 0, do not match.
extended global mask registers (08 ~ 0BH). This register is used to extend the message format, or XTD register packets set to 1, its role and ? the same.
bus configuration register (2FH):
COBY – bypass input comparator flag, active high.
POL – Polarity flag. 1, if the bypass input comparator, RX0 dominant input logic 1, logic 0 is hidden; to 0, and vice versa.
DCT1 – TX1 Output off control bit. To 1, TX1 output will not be driven, the model case for a bus, two differential wires short-circuit; to 0, TX1 outputs are driven.
DCR1 – RX1 input off control bit. To 1, RX1 comparator inverting input terminal disconnect, connected to VCC / 2; to 0, RX1 comparator connected to the inverting input terminal.
DCR0 – RX0 input off control bit. Role and DCR1 the same time RX0 phase comparator connected to the terminal.
Bit Timing Register 0 (3FH);
SJW – Synchronization Jump Width field, programmed value of 1 to 3.
BRP – baud rate divisor bit field, programmed value of 0 to 63.
Bit Timing Register 1 (4FH):
SPL – sampling mode flag. 1 for each sampled 3 times; 0 1 for each sample.
TSEG1 – time a field, programmed value of 2 ~ 15.
TSEG1 – time two games, programming a value of 1 to 7.
Baud rate = XTAL / [(DSC +1) * (BRP +1) * (3 + TSEG1 + TSEG2)]
message register (1 of each byte of the address register as the base address BASE).
BASE +0 MSGVALTXIERXIEINTPND
BASE +1 RMTPNDTXRQSTMSGLST / CPUUPDNEWDAT
Control Register 0,1 (BASE +0, BASET +1)
MSGVAL – register valid flag messages, active high. 10 set, 01 reset.
TXIE – Send interrupt enable flag, active high. 10 set, 01 reset.
RXIE – Receive interrupt enable flag, active high, set 10, 01 reset.
INTPND – interrupt request flag, active high. 10 set, 01 reset.
RMTPND – apply for remote frame flag, active high. 10 set, 01 reset.
TXRQST – request flag, active high. 10 set, 01 reset.
MSGLST – packet loss flag is only used to receive the message registers. 10 newspaper article that is not covered by the new message, 01 that are not covered.
CPUUPD – CPU update flag is only used to send the message registers. 10 packets being sent 01 messages can be sent.
NEWDAT – new data flag. 10 that new data written to the register, 01, said no new data is written.
arbitration register 0,1,2,3 (BASE +2- BASE +5)
Stored message identifier.
message configuration register (BASE +6)
DLC – Data length code, the programming value of 0 ~ 8.
DIR – Direction flag. 1 sent, 0 received.
XTD – standard / extended identifier flag. 1 Extended Identifier, 0 standard identifier.
Data register (BASE +7- BASE +14)
82527 store messages, the 8 data bytes are written, unused bytes of data is random.
2 Hardware Design
Intelligent node of the circuit shown in Figure 1 (shown in 6264 spent).
In the hardware design, by the ADC0809 complete set of 8 analog conversion, and the 8051 inquiry by way of exchange of information, address BFF8 ~ BFFFH, half the clock frequency obtained by ALE; 82527 to complete the exchange of information with the CAN bus. In this design, bypass the input comparators, with the 8051 information exchange with interrupt, the address 7F00 ~ 7FFFH, you can use 82527 the P1 and P2 port on the switch ports collection or relay control. 82C250 provides 82527 and the physical interface between the bus and improve the ability to receive and send. Program memory can be expanded as needed.
3 Software Design
The design software with MCS-51 assembly language, the block diagram shown in Figure 2.
82527 initialization procedure is as follows:
INT: MOV DPTR, # 0FF02H
MOV A, # 00H
MOVX @ DPTR, A; SCLK = XTAL
; MCLK = SCLK, CLKOUT valid
MOV DPTR, # 0FF00H
MOV A, # 41H
MOVX @ DPTR, A; set CCE, INIT
MOV DPTR, # 0FF2FH
MOV A, # 48H
MOVX @ DPTR, A; bypass input comparator to set a hidden, 0 is dominant, RX1 invalid
MOV DPTR, # 0FF3FH;
MOV A, # 43H;
MOVX @ DPTR, A; SJW = 2, BRP = 3
MOV DPTR, # 0FF4FH
MOV A, # 0EAH
MOVX @ DPTR, A; SPL = 1, TSEG1 = 7, TSEG2 = 6 then the baud rate is 100Kbps
MOV DPTR, # 0FF00H;
MOV A, # 01H
MOVX @ DPTR, A; prohibit access to the configuration register
MOV DPTR, # 0FF10H;
MOV A, # 55H;
MOVX @ DPTR, A;
MOVX @ DPTR, A;
MOV DPTR, # 0FFF0H;
MOV A, # 55H;
MOVX @ DPTR, A
MOVX @ DPTR, A; control bit register initialization packet
MOV R0, # 06H;
MOV DPTR, # 0FF06H;
MOV A, # 0FFH;
L1: MOVX @ DPTR, A; all matching message identifier to be
DJNZ R0, L1;
MOV DPTR, # 0FF16H;
MOV A, # 8CH; message register 1 can be extended to send packets 8 bytes
MOVX @ DPTR, A;
MOV DPTR, # 0FF26H;
MOV A, # 84H;
MOVX @ DPTR, A; Register 2 packets 8 bytes can be extended to receive packets
MOV DPTR, # 0FF00H;
MOV A, # 00H;
MOVX @ DPTR, A; Initialization end