Sample and Hold Amplifier AD 9100 interface circuit test board

Figure shows the AD9100 interface to the test board circuit . AD9100 input signal VIN 4 feet, to keep the built- in capacitor and switching devices , the signal through the sample and hold amplification from 9 feet out directly through the AD9620 can also be the output buffer stage . Clock input "CLOCK IN" Add Analog Devices AD96685 Ultrafast comparator input of the same phase , Q, Q output is sent to non- AD9100 ‘s CLK and CLK non ( 19,18 feet ), as a sample and hold control signal . With 0.01µF capacitor C1 ~ Cl0 , C13, Cl4 use tantalum capacitors . When connected to TTL clock signals W1 , W2 when connected to the reference signal .