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PWM A- D converter circuit using MCU

Published on Aug 12 2010 // Micrcontroller circuits

PWM A - D converter circuit using MCU

Abstract :Give a comparison using COP820CJ chip design it based on pulse modulation of the A / D converter design, are given by using software to adjust the A / D converter input voltage of the procedures and methods. Keywords :PWM A / D transform count COP820CJ 1 COP820CJ chip introduced COP820CJ National Semiconductor is a production of 8-bit microcontroller , which contains 64 bytes of RAM and 1k bytes of ROM, and with 24 I / O port , the clock frequency of 10MHz, operating voltage 2.5 ~ 6.0V. COP820CJ with multi-input wake-up (MIWU), low voltage reset protection, on-chip analog comparator and design features low electromagnetic radiation , its I / O port programmable as the three-state , push-pull output , weak pull-up and other types of input . COP820CJ port is divided into L / I / D / G four . Where I exit for the four input ports , D port for the four output ports , G I have six I / O ports and two inputs , L population of 8-bit I / O port . L is also a chip at the same time I wake up the port , in which L1 and L2 is the comparator input , L3 is the comparator output. L port with a data register (LDATA [0DOH]) and the configuration register (LCONF [0D1H]), two registers may jointly determine the status of the port . Table 1 lists the specific relationship . COP820CJ -chip RAM, the port , register 00H ~ FEH can be mapped to data memory space , which C0 ~ CFH is a wake-up and use the main section of the watchdog control register , D0 ~ DFH Section 8 ports class registers , E0 ~ EFH Segment register for the timer and the system . 00 ~ 2FH and F0 ~ FFH for the RAM address . Which , F0 ~ FEH section can be used as registers , and includes the B address register [FCH], X address register [FEH] and the SP stack pointer [FDH] three dedicated registers . 2 COP820CJ works 2.1 Basic Principles Use COP820CJ chip analog comparator and pulse width modulation control by software and may constitute a variable input range A / D converter. The working principle is shown in Figure 1 below. The figure , L1 and L2 for the comparator input , when the capacitor voltage is less than the input voltage , L3 -side output high pulse . On the contrary , L3 output low pulse , and by a low pulse count . Circuit voltage can be L1, L2 back diodes between the two parallel rapid charge and discharge the capacitor C1 , so that the two potential rapidly approaching . Comparison allows the input voltage is 0.4V ~ Vcc-1.5V ( at this time and the charge capacitor voltage , discharge time was approximately linear relationship between ) , the actual input voltage range may be even smaller . Therefore , you can set the parameters of high and low pulse to the capacitor voltage is always maintained in the measurement range. If the power is 5V, the clock frequency of 10MHz, pulse period of 24 months , or 2.4µs,Input voltage range is 1.0V ~ 3.3V. So , you can set the high pulse for the first 8 clock low , then high 16 clock ; set low pulse for the first 5 clock high , then low 19 clock . Thus, if the L3 is always the output of high pulse , the capacitor voltage VH to approximately Vcc × 16/24 = 3.30V; if L3 has the output low , the capacitor voltage VL is approximately Vcc × 5 / 24 = 1.04V. For A / D conversion , L3 level according to results of the comparison output pulse , when the pulses long enough , the counter value that represents the input voltage , and can be expressed as : VIN = VL + (VH-VL) (NTON / NTOTAL) Which , NTON the counter value , NTOTAL the total number of pulses . 2.2 conversion time and resolution As the pulse period of 2.4µsIf the total number of 100 pulses , then, for two counts of conversion time is approximately 2.4 × 100 × 2 = 480µs. When the input signal for high-speed change , can only reduce the total number of pulses . If a total of 100 pulse , input voltage of 1.0 ~ 3.3V, the resolution of 23mV. To improve the resolution of the input signal can be rough the first test, then adjust the high and low pulse duty cycle , in order to slightly exceed the measured voltage corresponding to the upper and lower limits , so you can get higher resolution. 3 Software Design Figure 2 shows the design with COP820CJ A / D converter work flow chart. Among them, the control register 2 (CNTRL2 [CC]) is the third comparator allows bit , fourth bit comparator output . X commands for the exchange of data in two registers . "SBIT (RBIT) i, n" n order to register for the location of the first i 1 ( 0). "IFBITi, n" directive in the n i- bit register 1, to execute an instruction , otherwise skip . "DRSZ n" is the role of instruction n the value of the first register by one , such as the results of non-zero , then the next instruction , otherwise skip . To ensure that the clock pulse period of 24 months , to be precise calculation instruction cycle . The instruction clock cycle , respectively : NOP: 1 clock ; SBIT / RBIT / IFBIT ( on the B, X register operation ) : a clock ; DRSZ / JP: 3 clock . A compilation of specific procedures are as follows : (B = LDATA) SBIT 4, CNTRL2; allow the work of the comparator LD LCONF, # 00 LD LDATA, # 00; home port for the high impedance input L CONV: LD A, # 02 LD 0F1, # 02; record number of LD TOTAL, # 064 LD TON, # 064; counter initial value SBIT3, [B] SBIT 3, LCONF; make L3 output 1 LOOP: IFBIT3, CNTRL2 JP HIGH; such as the comparator output is 1 , then jump NOP NOP; delay to the start time point consistent with high and low pulse SBIT 3, [B]; low pulse part . L3 clock set high five DRSZ TON; TON minus 1 NOP RBIT 3, [B]; L3 home is about 19 clock NOP NOP JP COUNT HIGH: RBIT3, [B]; high pulse part . L3 8 set clock low NOP NOP NOP NOP NOP NOP SBIT 3, [B]; set high 16 clock NOP NOP COUNT: DRSZ TOTAL; TOTAL counter by 1 JP LOOP RBIT 3, LCONF RBIT 3, [B]; home L3 for the high impedance input to prevent errors IFEQ A, 0F1 JP RELOAD; for the first time the counter to zero is to RELOAD JP DEC; or to the DEC RELOAD: LD TON, # 064 LD TOTAL, # 064; re- load counter DEC: SBIT 3, [B] SBIT 3, LCONF make L3 output 1 DRSZ 0F1 JMP LOOP; a second count LD A, TON X A, 00; save TON to RAM00H END