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Parallel communication circuit of CPLD MCU with ISA bus

Published on Oct 29 2010 // Micrcontroller circuits


Parallel communication circuit of CPLD MCU with ISA bus circuit

Abstract: ALTERA company MAX7000 series CPLD chip MCU and PC104 ISA bus interface, parallel communication between the given system design method and program source code. Including communications software and AHDL design component.
CPLD (Complex Programmable Logic Device) is a complex programmable logic device users, the use of a continuous connection structure. This structure is easy prediction latency, thus more accurate circuit simulation. CPLD is the standard large scale integrated circuit products can be used for a variety of digital logic design. In recent years, due to the integration of advanced technology and mass production, CPLD device costs continue to decline, integration density, speed and performance greatly improved, a chip can implement a complex digital circuit system; coupled with easy to use development tools using CPLD devices can greatly shorten the product development cycle, to design, modify, great convenience [1]. In this paper, ALTERA’s MAX7000 series, for example, to achieve MCS51 MCU and PC104 ISA bus parallel communication. With this communication, data transmission and accurate, high-speed, 12 MHz crystal in the MCS51 microcontroller data acquisition system, to meet with the PC104 ISA bus interface real-time communication requirements, communication speeds up to 200 Kbps.
An overall system design
The systems CLPD SCM and PC104 ISA bus interface parallel communication. PC104 mainly because other aspects of data collection to complete the work, but when they are free to receive data sent by MCU, it requires both a strong real-time communication, but the amount of data is not great. Therefore, the design of microcontroller interrupt in the system to receive data, PC104 to receive data using queries. System design shown in Figure 1.

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MCU part in Figure 1, D [0 .. 7] is a data bus, A [0 .. 15] is the address bus, RD and WR are the read-write signal line, INT0 external interrupt is a single chip. When the MCU external interrupt signal is active, the MCU receives the data.
In the CPLD part, by a MAX7000 series EPM7128LSC84 to achieve, to complete the MCS51 and PC104ISA data transfer between the bus interface, status inquiries and delay to wait.
Part of the PC104 ISA, ISA uses only 8-bit data bus D [0 .. 7], A [0 .. 9] is the PC104 address bus; IOW and IOR is to specify the equipment to read and write signals; AEN is allowed DMA control address bus, data bus and DMA transfers to read and write command lines, and the memory and I / O devices read and write; IOCHRDY is the I / O Ready signal, I / O Channel Ready is high, this time resulting processor Memory read and write cycle is 4 clock cycles, the resulting I / O read and write cycles and DMA byte transfer required five clock cycles, MCS51 by setting this signal low to insert wait to make CPU cycles, thus extending the I / O cycle; SYSCLK is the system clock signal, in order to keep pace with external devices; RESETDR is initialized on reset or system logic, the system is always clear signal.
2 Based on MAX + plus II’s hardware
This system is the company’s CPLD development tools ALTERA MAX + plusII. It supports multiple input methods, to the design and development to provide a great convenience. The main part of the system is still schematic way. Now the library is provided in the chip, so very easy to use. Schematic section shown in Figure 2 and Figure 3. Figure 2, mainly to complete single chip with the ISA interface, data transfer and communication handshake judge.

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D [0 .. 7] 8-bit microcontroller bidirectional data bus;
PCD [0 .. 7] ISA interface, 8-bit bidirectional data bus;
PCRD ISA interface to read valid signal;
PCWR ISA interface to write valid signal;
Determine the MCU has data to write data or read away;
PCSTATE microcontroller with the query data ISA interface is removed;
MSCRD read valid signal microcontroller;
MCSWR write effective signal microcontroller;
INT0 external interrupt signal microcontroller;
When MCUWR signal is valid, the MCU latches the data on the 74LS374 (1), this time, PCSTATE goes high. PC104 STATE strobes with a 74LS244 to determine whether the data bit PCD0 high, if it is high, indicating the MCU data sent, then the PCRD effective, from the data register 74LS374 (1) the removal of the data. At this point, PCSTATE goes low, the microcontroller by judging the signal is low to determine the PC104 has removed the data, you can send the next data.
After the signal is valid when the PCWR, PC104 in the data latch 74LS374 (2), this time, INT0 leap into a low power, single chip generate an external interrupt, so MCSRD signal is valid, from the data latch 74LS374 (2) the removal of decoration, INT0 goes high. PC104 STATE strobes with 74LS244 determine whether the data bit PCD1 high, if it is high, indicating that removal of the SCM data, you can send the next data. PC104 communicate with the microcontroller, the most critical is the speed of matching. As fast as PC104, the slower the microcontroller, therefore, to be inserted in the PC104’s IOCHRDY waiting period, as shown in Figure 3.
IOCHRDY ISA interface, used to wait 5 clock cycles;
DLY_D delay the input signal;
DLY_CK delay waiting for the clock signal;
DLY_CLR waiting for clear signals to begin the next cycle to prepare to send a few;
DELAY delay of 5 clock cycles after the output signal, as DLY_CLR signal input;
SYSCLK ISA interface to the system clock signal.
MCS51 communicate with the PC104 in the process, DLY_D signal has been effective (high). SYSCLK role in the signal, each clock cycle 5 a DELAY signal is valid, that is high. At this point DLY_CLR signal active (low), IOCHRDY signal goes high, PC104 can read and write data.
Address decoding part is the text input mode, with the ALTERA company’s hardware design and development language AHDL (Altera Hardware Description Language). AHDL is a modular high-level language, fully integrated in MAX + plusII system, particularly suitable for describing the complex combination of logic, state machines, and truth table, part of the address decoding a text input methods, which fully reflects the text input approach has the advantage. Enter the text as follows:
SUBDESIGN Address
(
PCA [9 .. 0]: INPUT;
AEN, IOR, IOW: INPUT;
RESETDR, DELAY: INPUT;
A [15 .. 14]: INPUT;
RD, WR: INPUT;
DLY_D: OUTPUT;
DLY_CK: OUTPUT;
DLY_CLR: OUTPUT;
STATE: OUTPUT;
PCRD: OUTPUT;
PCWR: OUTPUT;
MCURD: OUTPUT;
MCUWR: OUTPUT;
)
BEGIN
! DLY_CLR = RESETDR # DELAY;
DLY_D =! AEN & (PCA [9 .. 1] = = H “110”);
DLY_CK =! AEN & (PCA [9 .. 1] = = H “110 “)&(! IOR #! IOW);
! PCWR =! AEN & (PCA [9 .. 0] = = H “220”) &! IOW;
! PCRD =! AEN & (PCA [9 .. 0] = = H “220”) &! IOR;
! STATE =! AEN & (PCA [9 .. 0] = = H “221”) &! IOR;
! MCSRD = ([15 .. 14] = = H “1”) &! RD;
! MCSWR = (A [15 .. 14] = = H “2” &! WR;
END;
Description: PCA [9 .. 0] is the PC104 address signals, A [15 .. 14] is a single chip address signal, PC104 uses port address 220H and the 221H.
3 Communication Software
PC104 is based on the ISA bus in system software design to prevent address conflicts. PC104 using the address bits A0 ~ A9, said I / O port address, you can have port 1024 Address: 512 for the system board before use, after the 512 slots available for use. When A9 = 0 for the system board, said the port addresses; A9 = 1, it indicates that the interface card expansion slot port address [2]. Therefore, the use of reserved port addresses 220H and 221H, guaranteed not to address conflict.
PC104 uses the program to receive query data, microcontroller with interrupt receiving data.
# Define pcreadwrite 0x220 / * PC104 read and write data port address * /
# Define pcrdstate 0x221 / * PC104 Check status port address * /
PC104 write data function:
Void pcwrite (int port, unsigned char ch)
{Outportb (pcreadwrite, ch);
while ((inportb (pcrdstate) & 0x02)! = 0x02); / * wait for data to go read MCU * /
{}
}
MCU read subroutine:
MCUWR: MOV DPTR, # 4000H
MOVX A, @ DPTR
RETI
PC104 read data function:
Unsigned char pcread (int port)
{While ((inportb (pcrdstate) & 0x01)! = 0x01); / * wait for MCU to write data * /
{}
return inportb (pcreadwrite);
}
Microcontroller to write a subroutine:
MCUWR: MOV DPTR, # 8000H
MOVX @ DPTR, A
; Wait to go read the data PC104
RET
4 Conclusion
CPLD MCU with ISA bus interface with parallel communication, simple structure, small size, a CPLD chip enough and easy to control, and real time, communications, and high efficiency. This design method has been successfully applied to the development of a variety of data acquisition systems for microcontroller and parallel data communications between the PC104, the effect is very satisfactory.