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Logic Level convertor circuit

Published on Aug 12 2010 // Conversion Circuits

Logic Level convertor circuit

Logic Level convertor circuit1

Logic Level convertor circuit 2

In the next-generation electronic product design , TTL level or 5V CMOS logic circuits are no longer occupy the dominant position . With the introduction of low-voltage logic , often occur within the system input / output logic uncoordinated , and thereby improve the system design complexity. For example, when the 1.8V digital circuits and analog circuits work in 3.3V to communicate , you need to first solve the two -level conversion , this article describes the different logic level conversion method between . A need for logic level conversion As the number of different voltage IC ‘s continue to emerge , the need for logic level conversion is more prominent ways to level conversion logic voltage with the data bus in the form of (for example, 4-wire SPI, 32 -bit parallel data bus , etc.) and Different data rates change . While many logic chips can now achieve a higher logic level to a lower logic level conversion (such as 5V to 3V level translators level ), but very few logic chips to low logic level conversion Into a high logic level (eg 3V to 5V logic conversion logic) . In addition , although the level converter can also use transistors or resistance – diode combination to achieve , but the parasitic capacitance due to the impact of these methods greatly limits the data transmission rate . Despite the wide- byte level converters have been commercialized , but these products are not lower than the 20Mbps data rate for serial bus (SPITM, I2CTM, USB , etc.) optimized , these devices have a larger package size , more Pin count and I / O direction control pin , and is not suitable for small or peripheral serial bus interface and a higher rate ( such as Ethernet , LVDS, SCSI , etc.). SPITM ( Serial Peripheral Interface ) are generally one-way line of control , data input , data output , clock and chip select component , data input / output also can be a MISO ( master input slave output ) and the MOSI ( master output, from Machine input) . SPI clock rate of more than 20Mbps, by the logic CMOS push-pull output stage driver . Unidirectional data transfer simplifies the converter design. Because the data do not consider a single two-way signal transmission line problems , therefore, can use a simple resistor as shown in Figure 1 – diode or transistor programs the program . Bi-directional level translation bus need to consider in a single bi-directional signal lines for data transmission , which is difficult when the specific implementation , the resistance – diode structure or a single transistor by its solid as a one-way transmission characteristics can not be equal to the constraints Work . I2C, SMBus, Dallas Semiconductor 1-wire bidirectional transmission bus survived , while all open-drain I / O topology . I2C speed range which has three were less than 100kbps of standard mode , fast mode of less than 400kbps and less than 3.4Mbps high-speed mode . Click to enlarge 2 -way level translation In the way level translation devices , for those able to convert a high logic level low logic level devices , IC manufacturers provides a device which allows the input range, within the specified input range , the device can be Input clamping voltage tolerance within in the past . As with input over-voltage protection of logic Qijian affordable input voltage higher than its supply voltage , therefore , these devices simplify the logic level Zhi Gao low logic level (Vcc logic level ) and conversion solutions . In the high fan-out or high capacitive load connector design, any logic device , while reducing the supply voltage , the output drive capacity decreases only 3.3V CMOS / TTL and 5V TTL conversion between standards is A special case . As 3.3V and 5V logic Ae logical limit is the same. SPI bus requires both a high logic level to low logic level conversion , also need to convert the logic level low to a high logic level . For example, the processor logic with 1.8V to 3.3V when the peripheral logic . Of course, the use of the discrete scheme can achieve this conversion, but the MAX1840/MAX1841 , or MAX3390 single-chip solutions such as equipment can be greatly simplified the process shown in Figure 2 . 3 bi-directional level translation Through the parallel bus level translation , because usually there is WR and RD signals , which can use the bus switch ( such as 74CBTB3384) to implement different logic levels between the data connection. For a single bus or 2 -wire interface , the general need to consider two questions : First, a separate enable pin to control the data flow control ( occupied effective control port) , and second, larger chip size ( occupying a larger circuit board Size) . There is any design , anti- two directions of , but designers usually hope that it can work in any logic level , that is, hope it can achieve a high-voltage logic from the logic of conversion to low voltage , but also low- Voltage logic high voltage conversion logic can accomplish the level of one-way conversion , but also the completion of bi-directional level translation of common devices . A new generation of bi-directional level shifter can be qualified for the MAX3370 work , whether it works in low- voltage logic , or work in high-voltage logic , may rely on external output drive current to achieve the level of respirable conversion gate transmission ( Figure 3) . These structures enable the device can work in open-drain output stage can also be work area work area for the push-pull output stage . Moreover , MAX3370 with peptone very low resistance (less than 135O), the impact of the data transmission rate is small . Figure 3 shows the MAX3770 ‘s internal structure , the device has two advantages: First of all open-drain topologies , MAX3370 internal 10kO pull-up resistor and the " speed "switch the parallel circuit not only eliminates the need for external pull-up components , but also by As the RC time constant smaller ripple caused . In most open-drain output circuit , the data rate by the RC time constant greater impact . The unique " speed up " the structure of the MAX3770 is greatly improved data on the rising edge of the pull speed , reduces the impact of capacitive load , which allows data rates up to 2Mbps, which greatly improved the performance of traditional design ; Secondly, since the MAX3370 Device is tiny SC70 package, therefore , saving board space. MAX3370 can achieve the minimum 1.2V, maximum 5.5V logic level conversion , to meet the vast majority of equipment on the level conversion requirements. It must be explained : MAX3370 provides only one-way general-purpose logic level conversion . If the design of multiple I / O port line , you should choose another chip parameter table 1 . Table 1 logic level converter With the system I / O voltage increase in the number , level conversion of the design is also more complex. Taken into account when designing capacitive load , Vcc pressure range and data rate issues. The logic level from high to low logic level conversion , as long as the guarantee level pressure change in the Vcc line device can be allowed tolerance . In dealing with the logic low voltage logic high voltage conversion , and while there is a big Vcc pressure , the problem will become very difficult . Bi-directional level translation or open-drain output structure are greater constraints on the data rate , while Maxim ‘s level converter circuit is to use its unique structure simplifies the design of level conversion . It can achieve a wide voltage range of -way , bi-directional level translation , and provide open drain or push-pull output Zan . These devices use tiny package, does not require any external components , while significantly saving circuit board space .