Abstracthow to implement PC and SCM systems, high-speed data communications, measurement and control system is frequently encountered problems. This article introduces the use of EPP system to achieve high-speed data communication interface protocol principles, and from the hardware, software applications both EPP interface protocol gives a design example.
SCM system often requires the function of communication with the PC, to facilitate the microcontroller in the data to PC, used statistical analysis; sometimes you need to load the data in PC-SCM systems, verification of the microcontroller program and debugging. The commonly used means of communication is a serial communication, but the transmission rate is too low to calculate 9600bps, transfer 1MB at least 10min (minutes) or more. Parallel communication serial communication to overcome the shortcomings of low transmission rate. Standard Parallel Port SPP (Standard Parallel Port) mode achieved by the PC, one-way transmission to the peripherals, but the realization of PC, peripheral sent the data received is very cumbersome;The Enhanced Parallel Port EPP (Enhanced Parallel Port) protocol is a good solution to this problem, to achieve a stable high-speed data communications.
A, EPP interface protocol description
EPP protocol was originally developed by Intel, Xircom, Zenith made three companies in 1994, published in the IEEE1284 standard. EPP protocol has two standards EPP1.7 and EPP1.9. Centronics parallel port with the standards of the traditional use of different software handshake, EPP automatically by the hardware handshaking interface protocol, can reach 500KB s ~ 2MB s communication speed.
1.EPP pin definition
EPP pins as defined in Table 1.
Table 1 EPP connector pin definitions
Pin No. SPP Signal EPP Signal Direction Description
1 Strobe nWrite Output Indicating that the host is written to the peripheral (low) or read from the peripheral (high)
2 to 9 Data0 ~ 7 Data07 Input Output Bi-directional data bus
10 Ack Interrupt Input Falling edge interrupt to the host application
11 Busy nWait Input Low that the peripheral is ready to transfer data, the number transfer is complete, said high
12 PaperOut End Spare Input Free line
13 Select Spare Input Free line
14 Autofd nDStrb Output Data strobe, active low
15 Error Fault nDStrb Input Free line
16 Initialize Spare Output Initialization signal, active low
17 Selected Printer nAStrb Output Address data strobe, active low
18 ~ 25 Ground Ground GND Ground
2.EPP Interface Timing
EPP use of hardware to achieve automatic handshake between the host and the peripheral speed bidirectional data transfer, the software only on the corresponding port register read write operations.
(1) EPP write operation sequence shown in Figure 1.
CPU write data to the peripheral implementation steps are as follows
? program EPP data register is written;
? nWrite set low;
? CPU will be valid data to the data bus;
? nDStrb (nAStrb) to low (as long as nWait low);
? Wait nWait host becomes higher, confirm that the data sent successfully;
? wait nWait host becomes higher, confirm that the data sent successfully;
? EPP write cycle.
(2) EPP read operation timing shown in Figure 2.
CPU read data from a peripheral steps are as follows
? program corresponding port register is read EPP;
? nDStrb (nAStrb) is set low (if nWait low);
? Wait nWait high host to confirm successful data transmission;
? the host to read data from the parallel port pins;
? nDStrb (nAStrb) is set high;
? EPP read cycle.
3.EPP port register
Apart from SPP EPP interface, the three port register, it also added a 5-port registers, as listed in Table 2.
Address Port Name Direction
Base address +0 SPP data port Write
Base address +1 State port EPP Reading
Base Address +2 EPP control port Write
Base address +3 EPP Address Port Read Write
Base address +4 EPP Address Port Read Write
Base address +5 EPP data port Read Write
Base population +6 Undefined (32-bit transfer) Read Write
Base address +7 Undefined (32-bit transfer) Read Write
EPP Status Port Register
WAIT INTR USER1 USER2 USER3 × × TMOUT
WAIT Wait State bit (a valid);
INTR Interrupt request status bit (a valid);
USER1 ~ USER3 user-defined;
TMOUT reserved (EPP1.7) Time-out bit (EPP1.9).
EPP control port register.
× × DIR IRQEN ASTRB INIT DSTRB WRITE
DIR Direction bit (1 input, 0 output);
IRQEN interrupt enable bit (a valid);
ASTRB address strobe bit (0 active);
INIT Initialize (1 active);
DSTRB Data strobe bit (0 active);
WRITE read write status bit (0 write, 1 read).
Read the interface status and control interfaces are only required to register on the corresponding port operations. To initialize an example
Read initialization outportb (port +2,0 x24);
Port data port address for the SPP
Write initialization outportb (port +2,0 x04);
Port +2 control port address for the EPP
4.EPP1.7 and EPP1.9
There EPP1.7 EPP standard definition of the interface first, because due to hardware manufacturers, EPP two existing standards EPP1.7 and EPP1.9, can BIOS peripherals Parallel Port (BIOS Peripheral Setup Parallel Port Mode ) mode settings. There are differences between the two
(1) EPP lowest state of the port register bit0, in EPP1.9 defined as TMOUT. Operation timing in the EPP, if the PC, the data (address) after the strobe goes low, and in the 10µs time, failed to nWait peripheral set to low, then TMOUT set to 1, that delay.
(2) EPP1.9 standard, only when nWait is low, can start an operating cycle; but EPP1.7, no matter nWait status, nAstrb (nDstrb) will be set low, thereby starting a new data ( address) operating cycle.
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