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Design of Digital Responder circuit

Published on Aug 23 2010 // Modulator Demodulator circuits

Design of Digital Responder circuit

Design of Digital Responder1

Design of Digital Responder2 

Design of Digital Responder3

First, the design tasks and requirements 1 . Responder same time for eight players or eight team competition , with eight buttons were S0 ~ S7 said . 2 . to set clear and the answer in a system control switch S, the switch controlled by the moderator . 3 . Responder has a latch and display . The player press the button , latch the corresponding number , and digital tube LED display , audible alarm speaker also prompt . Players answer in the implementation of the priority latch , first answer in player numbers has been maintained to host the system cleared. 4 . Responder Responder with a timer function , and an answer in the time set by the host (such as 30 seconds). When the host start the "Start" button , the timer for less time , while a short sound loudspeakers , sound lasted about 0.5 seconds . 5 . players in the set to answer in time , answer in an effective , timer stop working , the display shows player number and answer in time to host and maintain the system cleared. 6 . If the timer time is up, no answer in the second answer in an invalid , and to prohibit Responder Alarm , time on the display 00 . Second , words, text 1 . Review Encoder , decimal addition / subtraction counter works. 2 . Design time can be preset timer circuit . 3 . Analysis and design of sequence control circuit . 4 . Draw time answering device machine logic circuit Third, design principles and reference circuit 1 . Overall block diagram of digital Responder Figure shows the overall block diagram . The working principle is: When powered on , the host will switch to the " clear "state , Responder is against state code displays off lights, set the timer display time ; host will switch set ? quot; start "state , announced the "Start" Responder work . timer countdown , the speaker gives an audible alert signal . players in the regular time, Responder , the Responder to complete : first determine , number latch , number display , speaker prompts . When a Responder , the Timer stop , against the second answer in , the timer displays the remaining time . If the host must again answer in another operation " Clear "and" Start "state switches . 2 . Cell design (1 ) Responder circuit Reference circuit as shown. To complete the circuit two functions: First, identify the sequence of key players , and the latch first answer in the number who , while decoding display circuit shows number; two key operation is ineffective against other players . Work process: switch S placed in the " clear " side when , RS flip-flop flip-flop output terminal are set to 0 0,4 months , so 74LS148 ‘s = 0 , so that in working condition. When the switch S placed in the " start ", the Responder in a state of waiting for work , when players will be key pressed (such as pressing the S5), 74LS148 latch output by the RS after , 1Q = 1, = 1,74 LS48 in Working state , 4Q3Q2Q = 101, by decoding appears as "5 . " In addition , 1Q = 1, so 74LS148 = 1, in a disabled state , blocking the input of other keys . When the release button is pressed , 74LS148 at this point as still 1Q = 1, so that = 1 , so 74LS148 still prohibit the state , to ensure that no input signal when a second button to ensure the Responder ‘s priority. If required by the host will once again answer in S switches back home ? quot; Clear " and then answer in the next round . 74LS148 8 Line Priority Encoder lines -3 , Table 11.1 of its menu. According to grab the answer from the presenter ‘s ease , set one answer in time , through the preset time, preset circuit on the counters , the counter ‘s clock pulse from the second pulse circuit. The circuit can be pre- selected time, add and subtract decimal counter 74LS192 synchronous design , the specific circuit shown above . (3 ) Alarm Circuit Posed by the 555 timer and alarm circuit transistor shown in Figure 11,4 . Which constitute a multivibrator 555 , the oscillation frequency fo = 1.43 / [(RI +2 R2) C], the output signal by the transistor to promote the speaker . PR for the control signal , when the PR is high , the multi- harmonic oscillator , the other hand, the circuit stops vibrating . 4) The timing control circuit Timing control circuit is the key answer in design , it is to complete the following three functions : ? The host will control the switch to " start "position , the speaker voice , answer in the circuit and timing circuit into the normal answer in working condition. ? When pressing the answer in key players , speakers, sound , answer in the circuit and timing circuit to stop working . ? When the set of answer in the time that no one answer in time , the speaker voice , and answer in the circuit and timing circuit to stop working . According to the above functional requirements and design of the timing control circuit as shown above. The figure, the gate G1 of the role is to control the release of the clock signal CP and the prohibition , the role of gate G2 is controlled 74LS148 input enable terminal . Figure 11,4 of the working principle is: host control switch from the " clear "position income into the " start "position, from Figure 11,2 of the 74LS279 ‘s output 1Q = 0, by the G3 RP , A = 1 , The clock signal CP can be added to the CPD 74LS192 clock input timing circuit for decreasing time . At the same time , the time not yet reached the time when the " time to signal " to 1, the output of gate G2 = 0 , so 74LS148 in normal working condition in order to achieve functional ? requirements. When the players answer in the time period of time pressed key , 1Q = 1, by G3 RP , A = 0, block CP signal , the timer is to keep working condition ; the same time, the output of gate G2 = 1,74 LS148 is in working condition prohibited To achieve the functional requirements of ? . When the regular time to time , the " time to signal "for 0, = 1,74 LS148 is in working condition prohibited , prohibited players to Responder . Meanwhile, the door is closed G1 state , blockade CP signal to timing circuit 00 to maintain the status quo, to achieve functional ? requirements. 74LS121 integrated monostable trigger circuit used to control the alarm and the sound of the time , it works on their own analysis of the reader . 4 , experimental equipment 1 . digital experimental box . 2 . IC 74LS148 1?, 74LS279 1?, 74LS48 3?, 74LS192 2?, NE555 2?, 74LS00 1?, 74LS121 1?. 3 . Resistance 510O 2?, 1KO 9?, 4.7kO l only , 5.1kO l only , 100kO l only , 10kO 1?, 15kO 1?, 68kO l only . 4 . Capacitor 0.1uF 1?, 10uf 2?, 100uf 1?. 5 . triode 3DG12 1?. 6 . Other: light-emitting diode 2 , common cathode display 3 . 5 , the content and method of experiment 1 . Debugging Responder circuit assembly . 2 . Design time can be preset timing circuit , and the assembly and debugging. When the input 1Hz clock pulse signal, the circuit can be reduced required time , when less time to zero, to output low effective time to signal timing . 3 . Alarm circuit debugging assembly . 4 . Completion of FBI time answering device , pay attention to the timing between the various parts of the circuit with the relationship . Then check the circuit functions of each part , to meet the design requirements .