ISFET (ion sensitive field effect transistors) can be used to measure the acidity of the fluid. Accurate measurement requirements ISFET bias conditions (ID and VDS) to maintain constant, direct contact with the gate while the measured fluid. The acidity of the fluid changes the channel width, resulting in a PH value of the fluid is proportional to the gate – source voltage VGS. Figure 1 circuit is a simpler and more accurate implementation. VA set by ISFET Q1 voltage drain current ID, and the drain voltage VB to set Q1 – source voltage VDS. High Precision Measurement of the two AD8821 amplifiers IC1 and IC2 are configured may have a gain equal to 1. IC3 is the AD8627 Precision JFET input amplifier, which buffers the drain voltage VD, to ensure that all current flows through R1 Q1.
Figure 1, the circuit for the ISFET (a sensor for measuring fluid acid) to provide the ideal bias.
To control ID, forcing its output amplifier IC1 and the differential between the reference input voltage is equal to the differential input voltage VA. Since the detected differential voltage is equal to the voltage across R1, so ID = VA/R1. When the R1 set to 20kO, ID can 50mA / V changes. Similarly, forcing the amplifier IC2 and the reference input output differential voltage between the differential input voltage is equal to the VB, thus forcing the VDS is equal to VB. (Note: If your design does not need a separate regulator VDS and ID, the circuit can be based on a control voltage to work. The VA and VB together, and the VDS with the required voltage to drive it. So R1 is equal to VDS / ID. ) the voltage VGS between the gate IC2 between voltage and output voltage. The circuit has a very useful feature, that the current source is floating, so that the gate voltage can be connected to the circuit within the scope of any common-mode voltage. VG range of the circuit (VA +2- VEE)
Figure 2 shows the configuration shown in Figure 1 when the circuit connected to the ADC has the advantages of the floating gate.
Figure 2 shows the type of the circuit connected to the AD7790 differential input S-ADC, have the advantages of the floating gate. Gate directly connected to the ADC reference voltage pin. VS (or VG) between the client and the ADC input signal conditioning circuit required only a simple RC filter is. In the current greater than 1mA, the resistor R1 in the current 0.1% error in the dominant source of error, therefore, when the drain current up to 250mA, R1 is less than 0.1% error is 250 nA. VDS is the error and gain error IC3 IC2 and IC3 of the input offset voltage generated. Drain – source voltage up to 2V, the drain – source voltage of the error is less than 450mV.