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8085 Instructions – control

Published on Oct 09 2009 // 8085 Instruction set


 Opcode  Operand Explanation of Instruction
 NOP none No operation No operation is performed. The instruction is fetched and decoded. However no operation is executed.

Example: NOP

HLT none Halt and enter wait state The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state.

Example: HLT

 DI none Disable interrupts

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected.

Example: DI

 EI none Enable interrupts

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).

Example: EI

 RIM none Read interrupt mas

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations.

Example: RIM

SIM none Set interrupt mask

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows.

Example: SIM